In the formation of fine-line MOS devices, a recurring and severe problem as the devices become smaller is hot carrier instability (HCI). This problem is related to the shorter channels of the smaller devices, such as when the channel length is 1 micron (um) or smaller, and occurs due to high electrical fields between the source and the drain, particularly near the drain that cause carriers, either electrons or holes, to be injected into the gate or substrate. The injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. Thus, HCI may also stand for hot carrier injection.
The effect of the high-charge levels in the thin gate dielectric is to shift the MOST field effect transistor (FET) device threshold, which makes it difficult or impossible for the FET device to operate correctly. HCI into gate insulators is a universal problem for small geometry FETs (channel lengths less than or equal to 1 um), since most hot carriers are trapped within approximately 100 Angstroms of the semiconductor surface.
This problem has been addressed by attempting to reduce the strength of the electric field near the source and the drain regions. One approach concerns using a graded drain structure, or graded source/drain (GSD). For instance, in an n-channel device, a heavily doped drain of phosphorus or arsenic surrounded by a lighter doping of phosphorus is used to gradually extend the drain region into the channel region to reduce the electric field strength right at the drain. However, this approach can be undesirable in that it causes larger overlap capacitance with the gate, larger lateral diffusion and channel shortening. Typically, merely the deeper junction of the drain produces more disadvantageous short channel effects, such as an abrupt dropoff of threshold voltage with L.sub.eff.
Further, the drain is preferred to be shallow and laterally graded as to profile as well as concentration. That is, it is desired for the drain profile to have a gradual decrease in surface concentration from the n.sup.+ regions 22 and 24 to the channel region 11, as depicted in the n-channel MOS field effect transistor (FET) 20 of FIG. 1. Less desirable is the profile shape shown in FIG. 2, where the source/drain regions exhibit similar lateral grading but with deeper vertical junctions. With deeper junctions, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, which causes "punch through current" problems and shorts out the device.
A known alternative to the graded source/drain structure is the use of lightly doped drains (LDDs). LDDs consist of a lightly doped source/drain region that is driven just under the gate region, while the heavily doped drain region is laterally displaced away from the gate by use of a sidewall spacer on the gate. LDDs are advantageous because they do not have problems with excess lateral or vertical impurity diffusion. However, the process for making LDDs is complex, and typically requires the formation of a sidewall spacer n the gate to provide the exact horizontal and/or lateral displacement of the lightly and heavily doped drain sections. That is, in LDDs, the n.sup.- portion of the source/drain region is aligned to the polysilicon gate edge, and the n.sup.+ portion of the source/drain region is aligned to a spacer edge.
Another alternative to these structures is a double diffused drain (DDD). This feature is similar to the graded source drain discussed above, except that in this case, arsenic and phosphorus are implanted together, or are introduced into the same area, and are diffused together to form the source/drain structure. That is, both the n.sup.- and n.sup.+ portions of the source/drain regions are aligned to the polysilicon gate edge. The process for making DDDs is very simple compared to that for making graded source/drains or LDDs in that the impurity introduction is performed essentially all at one time and the anneal for both phosphorus and arsenic is performed together. However, the disadvantage with the DDD structure is that due to cooperative diffusion effects, phosphorus tends to diffuse faster in the presence of high arsenic doping, even faster than phosphorus diffuses by itself. Thus, the typical DDD structure tends to appear like that shown in FIG. 2; the LDD tends to appear like that shown in FIG. 1. This undesirable effect that enhances the phosphorus diffusion discourages the use of arsenic and phosphorus together in a DDD, and phosphorus alone or GSDs and LDDs are used instead.
Shown in FIG. 2 is a prior art MOSFET 10 on a semiconductor substrate 12, such as silicon, covered by a thin gate dielectric material 14. Upon the thin gate dielectric material 14 is a patterned gate material 15, covered by thermal oxide layer 13, having opposing sides adjacent which are source/drain regions 16 through 19. It will be appreciated that the source/drain regions 16 and 18, and especially n.sup.- source/drain regions 17 and 19, are deeper than desired due to the accelerated phosphorus diffusion in the presence of arsenic, and thus these DDDs suffer from the same disadvantages as the graded source/drains with deep junctions discussed above.
It would be desirable if the MOSFET 10 would have source/drain regions with a profile more like the profiles shown by n.sup.+ source/drain regions 22 and 24 and n.sup.- source/drain regions 23 and 25 in an improved MOSFET 20 illustrated in FIG. 1. Here, the source/drain regions 22 through 25 have the desired profile, satisfactory lateral grading with shallow vertical junction depths. The edges of the source/drain regions also have sufficient concentration just beneath the gate. In the DDD structure of FIG. 2, the n-type impurity regions 17 and 19 are deeper into the silicon 12 region. It will be appreciated that in the structure of FIG. 1, the primary impurity concentration remains at the surface of the semiconductor substrate. It would thus be advantageous if a process could be devised which would produce source/drain regions that would help solve HCI effects, but also be less susceptible to unwanted diffusion, as well as be easy to manufacture.